AQD200CL4CHL010

200Gbps

SMF

10km

CS

0~+70℃

Yes

CMIS4.0

Storage   Temperature

Ts

-40

+85

Power   Supply Voltage

Vcc

-0.5

3.3

3.6

V

Data   Input Voltage –

Single Ended

-0.5

Vcc+0.5

V

Data   Input Voltage –

Differential

0.8

V

Operating Relative Humidity

RH

5

85

%

Receiver Damage Threshold, per Lane

Rxdmg

5.5

dBm

Operating case temperature

Tc

0

25

70

°C

Power supply voltage

Vcc

3.135

3.3

3.465

V

Power dissipation

PD

8

W

Electrical Signal Rate per   Channel

25.78125

GBd

Optical Signal Rate per   Channel

25.78125

GBd

Power Supply Noise

66

mVpp

Receiver Differential Data Output Load

100

Ohm

Transceiver Power   Consumption

8

W

Transceiver Power Supply   Total Current, Total

2560

mA

TP0 to TP5

The channel including the transmitter and receiver differential controlled impedance printed circuit board insertion loss and the cable assembly insertion loss.

TP1 to TP4

All cable assembly   measurements are to be made between TP1 and TP4 as illustrated in Figure

3. The cable assembly test fixture of Figure 4 or   its equivalent, is required for measuring the cable assembly specifications   in 802.3bj 92.10 at TP1 and TP4.

TP0 to TP2 TP3 to TP5

A mated connector pair has been   included in both the transmitter and receiver specifications defined in   802.3bj 92.8.3 and 92.8.4. The recommended maximum insertion loss from TP0 to   TP2 or from TP3 to TP5 including the test fixture is provided in

802.3bj 92.8.3.6

TP3

Unless specified   otherwise, all receiver measurements and tests defined in 802.3bj 92.8.4

are   made at TP3 utilizing the test fixture specified in 802.3bj 92.11.1.

Signaling Rate, Per Lane

TP1

25.78125

GBd

+/-   100 ppm

Differential pk-pk Input   Voltage

Tolerance

TP1a

900

mV

Differential Return   Loss(min)

TP1

Equation(83E-5)

dB

802.3bm

Differential to   common mode input return loss (min)

TP1

Equation(83E-6)

dB

802.3bm

Differential termination   mismatch

TP1

10

%

Module stressed input test

TP1a

Single-ended voltage   tolerance range

TP1a

-0.4

3.3

V

DC common-mode output   voltage

TP1

-350

2850

mV

Module stressed input test

Eye width

0.46

UI

Applied pk-pk sinusoidal   jitter

Table   88-13

802.3bm

Eye height

95

mV

Signaling Rate, Per   Lane(range)

TP4

25.78125 ±

100   ppm

GBd

Differential output   voltage

TP4

900

mV

Differential output return   loss (Min)

Differential to common   mode conversion

return loss (min)

Differential termination   mismatch

Common mode voltage

Transition Time (20% to   80%)

Eye   width

Eye height differential

TP4

228

mV

Vertical eye closure

TP4

5.5

dB

Signaling speed per lane

BRAVE

25.78125

Gbps

Data Rate Variation

-100

+100

ppm

Modulation format

NRZ

Lane_0/4 Center Wavelength

λC0

1294.53

1295.56

1296.59

nm

Lane_1/5 Center Wavelength

λC1

1299.02

1300.05

1301.09

nm

Lane_2/6 Center Wavelength

λC2

1303.54

1304.58

1305.63

nm

Lane_3/7 Center Wavelength

λC3

1308.09

1309.14

1310.19

nm

Total Average Output Power

Po

10.5

dBm

Side Mode Suppression   Ratio

SMSR

30

dB

Extinction Ratio

ER

4

dB

Average Launch Power each   Lane

Peach

-4.3

4.5

dBm

Transmit OMA each Lane

TxOMA

-1.3

4.5

dBm

Launch power in OMA minus   TDP, each lane

OMA-TDP

-2.3

dBm

Transmitter and Dispersion   Penalty per Lane

TDP

2.2

dB

Average launch power of   OFF transmitter

-30

dBm

Optical Return Loss   Tolerance

20

dB

Transmitter Reflectance

-12

dB

Transmitter eye mask   definition {X1, X2, X3, Y1,Y2, Y3}

{0.25, 0.4, 0.45, 0.25,   0.28, 0.4}

Signaling Speed per Lane

BRAVE

25.78125

Gbps

Data Rate Variation

-100

100

ppm

Lane_0/4 Center Wavelength

λC0

1294.53

1295.56

1296.59

nm

Lane_1/5 Center Wavelength

λC1

1299.02

1300.05

1301.09

nm

Lane_2/6 Center Wavelength

λC2

1303.54

1304.58

1305.63

nm

Lane_3/7 Center Wavelength

λC3

1308.09

1309.14

1310.19

nm

Damage threshold

Rxdmg

5.5

dBm

Average receive power each lane

Rxpow

-10.6

4.5

dBm

Receive Power (OMA) per Lane

RxOMA

4.5

dBm

Receive Power (OMA) per Lane

RxOMA

4.5

dBm

Unstressed Receiver Sensitivity   (OMA) per Lane

Rxsens

-8.6

dBm

Stressed Receiver Sensitivity (OMA)   per Lane

RXSRS

-6.8

dBm

Vertical Eye Closure Penalty

VECP

1.8

dB

Stressed J2 Jitter

J2

0.3

UI

Stressed J4 Jitter

J4

0.47

UI

LOS Assert

LOSA

-25

dBm

LOS De-Assert

LOSD

-15

dBm

LOS Hysteresis

0.5

dB

RSSI accuracy

-3

3

dB

Receiver reflectance

-26

dB

1

GND

Ground

1

1

2

CML-I

Tx2n

Transmitter   Inverted Data Input

3

3

CML-I

Tx2p

Transmitter Non-Inverted Data Input

3

4

GND

Ground

1

1

5

CML-I

Tx4n

Transmitter   Inverted Data Input

3

6

CML-I

Tx4p

Transmitter Non-Inverted Data Input

3

7

GND

Ground

1

1

8

LVTTL-I

ModSelL

Module Select

3

9

LVTTL-I

ResetL

Module Reset

3

10

VccRx

+3.3V Power Supply Receiver

2

2

11

LVCMOS-

I/O

SCL

Two-wire serial interface clock

3

12

LVCMOS-

I/O

SDA

Two-wire serial interface data

3

13

GND

Ground

1

1

14

CML-O

Rx3p

Receiver Non-Inverted Data Output

3

15

CML-O

Rx3n

Receiver   Inverted Data Output

3

16

GND

Ground

1

1

17

CML-O

Rx1p

Receiver Non-Inverted Data Output

3

18

CML-O

Rx1n

Receiver Inverted Data Output

3

19

GND

Ground

1

1

20

GND

Ground

1

1

21

CML-O

Rx2n

Receiver   Inverted Data Output

3

22

CML-O

Rx2p

Receiver Non-Inverted Data Output

3

23

GND

Ground

1

1

24

CML-O

Rx4n

Receiver   Inverted Data Output

3

25

CML-O

Rx4p

eceiver Non-Inverted Data Output

3

26

GND

Ground

1

1

27

LVTTL-O

ModPrsL

Module Present

3

28

LVTTL-O

IntL/ RxLOSL

Interrupt. Optionally configurable   as RxLOSL via the management

interface   (SFF-8636).

3

29

VccTx

+3.3V   Power supply transmitter

2

2

31

LVTTL-I

LPMode/ TxDis

Low Power Mode. Optionally

configurable as TxDis via the management   interface (SFF-8636).

3

32

GND

Ground

1

1

33

CML-I

Tx3p

Transmitter Non-Inverted Data input

3

34

CML-I

Tx3n

Transmitter   Inverted Data Input

3

35

GND

Ground

1

1

36

CML-I

Tx1p

Transmitter Non-Inverted Data Input

3

37

CML-I

Tx1n

Transmitter   Inverted Data Input

3

38

GND

Ground

1

1

34

CML-I

Tx3n

Transmitter   Inverted Data Input

3

35

GND

Ground

1

1

36

CML-I

Tx1p

Transmitter Non-Inverted Data Input

3

37

CML-I

Tx1n

Transmitter   Inverted Data Input

3B

38

GND

Ground

1B

1

39

GND

Ground

1A

1

40

CML-I

Tx6n

Transmitter   Inverted Data Input

3A

41

CML-I

Tx6p

Transmitter   Non-Inverted Data Input

3A

42

GND

Ground

1A

1

43

CML-I

Tx8n

Transmitter   Inverted Data Input

3A

44

CML-I

Tx8p

Transmitter   Non-Inverted Data Input

3A

45

GND

Ground

1A

1

46

LVCMOS/CML-I

P/VS4

Programmable/Module   Vendor Specific

4

3A

3

47

LVCMOS/CML-I

P/VS4

Programmable/Module   Vendor Specific

1

3A

3

48

VccRx1

3.3V   Power Supply

2A

2

49

LVCMOS/CML- O

P/VS2

Programmable/Module   Vendor Specific

2

3A

3

50

LVCMOS/CML- O

P/VS3

Programmable/Module   Vendor Specific

3

3A

3

51

GND

Ground

1A

1

52

CML-O

Rx7p

Receiver   Non-Inverted Data Output

3A

53

CML-O

Rx7n

Receiver   Inverted Data Output

3A

54

GND

Ground

1A

1

55

CML-O

Rx5p

Receiver Non-Inverted Data   Output

3A

56

CML-O

Rx5n

Receiver   Inverted Data Output

3A

58

GND

Ground

1A

1

59

CML-O

Rx6n

Receiver   Inverted Data Output

3A

60

CML-O

Rx6p

Receiver Non-Inverted Data   Output

3A

61

GND

Ground

1A

1

62

CML-O

Rx8n

Receiver   Inverted Data Output

3A

63

CML-O

Rx8p

Receiver   Non-Inverted Data Output

3A

64

GND

Ground

1A

1

65

NC

No   Connect

3A

3

66

Reserved

For future use

3A

3

67

VccTx1

3.3V   Power Supply

2A

2

68

Vcc2

3.3V   Power Supply

2A

2

69

LVCMOS-I

ePPS/Clock

1PPS PTP clock   or reference clock input

3A

3

70

GND

Ground

1A

1

71

CML-I

Tx7p

Transmitter   Non-Inverted Data Input

3A

72

CML-I

Tx7n

Transmitter   Inverted Data Input

3A

73

GND

Ground

1A

1

74

CML-I

Tx5p

Transmitter   Non-Inverted Data Input

3A

75

CML-I

Tx5n

Transmitter   Inverted Data Input

3A

76

GND

Ground

1A

1

1: GND is the symbol for   signal and supply (power) common for the module. All are common within the   module and all module voltages are referenced to this potential unless   otherwise noted. Connect them

directly   to the host board signal-common ground plane.

2:   VccRx, VccRx1, Vcc1, Vcc2, VccTx and VccTx1 shall be applied concurrently.   Supply requirements defined for the host side of the Host Card Edge Connector   are listed in QSFP-DD MSA. For power classes 4 and above the module   differential loading of input voltage pads must not result in exceeding   contact current limits. Each connector Vcc contact is rated for a

maximum current of 1500   mA.

3: All Vendor Specific,   Reserved and No Connect pins may be terminated with 50 ohms to ground on the   host. Pad 65 (No

Connect) shall be left unconnected within the module. Vendor specific   and Reserved pads shall have an impedance to GND that is greater than 10   kOhms and less than 100 pF.

4:   Plug Sequence specifies the mating sequence of the host connector and module.   The sequence is 1A, 2A, 3A, 1B, 2B, 3B. Contact sequence A will make, then   break contact with additional QSFP-DD pads. Sequence 1A, 1B will then occur

simultaneously,   followed by 2A, 2B, followed by 3A, 3B.

5:   Full definitions of the P/VSx signals currently under development. On new   designs not used P/VSx signals are

recommended to be   terminated on the host with 10k ohms.

6: ePPS/Clock if not used   recommended to be terminated with 50 ohms to ground on the host.

SCL and SDA

VOL

0

0.4

V

SCL and SDA

VIL

-0.3

VCC*0.3

V

VIH

VCC*0.7

VCC+0.5

V

Capacitance for SCL and SDA I/O signal

Ci

14

pF

Total bus capacitive load   for SCL and SDA

Cb

100

pF

200

pF

LPMode/TxDisable, ResetL,   ModSeIL and ePPS/Clock

VIL

-0.3

0.8

V

VIH

2

VCC+0.3

V

LPMode, ResetL   and ModSeIL

|lin|

360

μA

IntL/RxLOSL

VOL

0

0.4

V

VOH

VCC-0.5

VCC+0.3

V

ModPrsL

VOL

0

0.4

V

VOH