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Part No. | Data Rate | Fiber | Distance | Interface | Temp. | DDMI | CMIS |
AQD400CC4CHC002 | 425Gbps | SMF | 2km | LC | 0~+70℃ | Yes | CMIS4.0 |
Absolute Maximum Ratings
Parameter | Symbol | Min. | Typical | Max. | Unit |
Storage Temperature | Ts | -40 | 85 | °C | |
Supply Voltage | Vcc | -0.5 | 3.3 | 3.6 | V |
Operating Relative Humidity | RH | 5 | 85 | % |
Recommended Operating Conditions
Parameter | Symbol | Min. | Typical | Max. | Unit |
Operating Case Temperature | Tc | 0 | 70 | °C | |
Power Supply Voltage | Vcc | 3.135 | 3.3 | 3.465 | V |
Power Supply Noise | 66 | mVpp | |||
Power Dissipation | PD | 10 | W | ||
Electrical Signal Rate Per Channel | 26.5625 | GBd | |||
Optical Signal Rate Per Channel | 53.125 | GBd | |||
Receiver Differential Data Output Load | 100 | Ohm | |||
Fiber Length | 2000 | m |
Figure 1: Transceiver Block Diagram
Figure 2: Application Reference Diagram
As shown in Figure 1, the transmitter path of the transceiver contains an 8x50Gbps 400GAUI-8 electrical input with equalization (EQ) block, integrated electrical multiplexer, EML driver, EML lasers, optical multiplexer and diagnostic monitor. The integrated electrical multiplexer converts 8 channels of 50 Gbps (PAM4) electrical input data to 4 channels of 100Gbps (PAM4) CWDM optical signals, the optical multiplexer multiplexes them into a single channel for 400Gb/s optical transmission.
As shown in Figure 1, the receiver path of the transceiver contains optical de-multiplexer, four PIN photodiodes, trans-impedance amplifiers (TIA), integrated de-multiplexer and 8x50G 400GAUI-8 compliant electrical output blocks. The module optically de-multiplexes a 400Gb/s optical input into 4 channels of CWDM optical signals, and the integrated de-multiplexer converts 4 channels of 100Gbps (PAM4) CWDM optical signals to 8 channels of 50Gbps (PAM4) electrical output data.
The interface between QSFP-DD module and ASIC/SerDes is shown in Figure 2. The high speed signal lines are internally AC-coupled and the electrical inputs are internally terminated to 100 Ohms differential. All transmitter and receiver electrical channels are compliant to module 400GAUI-8 specifications per IEEE 802.3bs.
The control signal interface is compliant with QSFP-DD MSA. The following pin is provided to control module or display the module status: ModPrsL, IntL/RxLOS, ResetL, LPMode/TxDis. In addition, there is an industry standard two wire serial interface scaled for 3.3V LVTTL. The definition of control signal interface and the registers of the serial interface memory are defined in the Control Interface & Memory Map section.
Exposure to current surges and overvoltage events can cause immediate damage to the transceiver module. Observe the precautions for normal operation of electrostatic discharge sensitive equipment; Attention shall also be paid to limiting transceiver module exposure to conditions beyond those specified in the absolute maximum ratings.
Optical connectors include female connectors. These elements will be exposed as long as the cable or port plug is not inserted. At this time, always pay attention to protection.
Each module is equipped with a port guard plug to protect the optical port. The protective plug shall always be in place whenever the optical fiber is not inserted. Before inserting the optical fiber, it is recommended to clean the end of the optical fiber connector to avoid contamination of the module optical port due to dirty connector. If contamination occurs, use standard LC port cleaning methods.
General Electrical Characteristics
Parameter | Symbol | Min. | Typical | Max. | Unit |
Transceiver Power Consumption | 8 | 10 | W | ||
Transceiver Power Supply Total Current | 2600 | 3200 | mA | ||
AC Coupling Internal Capacitor | 0.1 | μF |
Test Point | Description |
TP0 to TP5 | This channel includes transmitter and receiver differential control impedance printed circuit board insertion loss and cable assembly insertion loss. |
TP1 to TP4 | All cable assembly measurements are made between TP1 and TP4 as illustrated in Figure 3. |
TP0 to TP2 TP3 to TP5 | A mated connector pair has been included in both the transmitter and receiver specifications defined in 802.3cd 136.9.3 and 136.9.4. The recommended maximum insertion loss from TP0 to TP2 or from TP3 to TP5 including the test fixture is provided in 802.3cd 136.9.3.2 |
TP2 | Unless specified otherwise, all transmitter measurements defined in 802.3cd 136.9.3 are made at TP2 utilizing the test fixture specified in Annex 136B. |
TP3 | Unless specified otherwise, all receiver measurements and tests defined in 802.3cd 136.9.4 are made at TP3 utilizing the test fixture specified in Annex 136B. |
Figure 3: IEEE 802.3cd 50GBASE-CR, 100GBASE-CR2 or 200GBASE-CR4 link
Figure 4: IEEE 802.3bs 400GAUI-8 compliance points TP1a, TP4a
Figure 5: IEEE 802.3bs 400GAUI-8 compliance points TP1, TP4
Parameter | Test Point | Min. | Typical | Max. | Unit | Conditions |
Signaling Rate, Per Lane (PAM4 Encoded) | TP1 | 26.5625 | GBd | +/- 100 ppm | ||
Differential Pk-Pk Input Voltage Tolerance | TP1a | 900 | mV | |||
Differential Input Return Loss (Min) | TP1 | Equation(83E- 5) | dB | 802.3bs | ||
Differential To Common Mode Input Return Loss (Min) | TP1 | Equation(83E- 6) | dB | 802.3bs | ||
Differential Termination Mismatch | TP1 | 10 | % | |||
Single-Ended Voltage Tolerance Range | TP1a | -0.4 | 3.3 | V | ||
DC Common-Mode Output Voltage | TP1 | -350 | 2850 | mV | ||
Eye Width | 0.22 | UI | ||||
Applied Pk-Pk Sinusoidal Jitter | Table 120E-6 | 802.3bs | ||||
Eye Height | 32 | mV |
High Speed Electrical Output Characteristics
ParamPareter | Test Point | Min. | Typical | Max. | Unit |
Signaling Rate Per Lane(Range) | TP4a | 26.5625 ± 100ppm | GBd | ||
Common Mode Voltage | TP4a | -0.35 | 2.85 | V | |
Differential pk-pk Input Voltage Tolerance | TP4 | 900 | mV | ||
Differential Input Return Loss (Min) |
TP4a | Equation(83E-5) |
dB | ||
Differential To Common Mode Input Return Loss (Min) |
TP4a | Equation(83E-6) |
dB | ||
Differential Termination Mismatch | TP4a | 10 | % | ||
Transition time (20% to 80%) | TP4 | 9.5 | ps |
Optical Characteristics
High Speed Optical Transmitter Characteristics
Parameter | Symbol | Min. | Typical | Max. | Unit |
Signaling Speed Per Lane | 106.25 | Gbps | |||
Modulation Format | PAM4 | ||||
Lane_1 Center Wavelength | λC1 | 1264.5 | 1277.5 | nm | |
Lane_2 Center Wavelength | λC2 | 1284.5 | 1297.5 | nm | |
Lane_3 Center Wavelength | λC3 | 1304.5 | 1317.5 | nm | |
Lane_4 Center Wavelength | λC4 | 1324.5 | 1337.5 | nm | |
Side-Mode Suppression Ratio | SMSR | 30 | dB | ||
Extinction ratio | ER | 3.5 | dB | ||
Total average launch power | 9.3 | dBm | |||
Average launch power | TxAVG | -3.3 | 3.5 | dBm | |
OMA per lane | TxOMA | -0.3 | 3.7 | dBm | |
Difference in launch power between any two lanes (OMAouter) |
4 |
dB | |||
Launch Power in OMA-TDECQ for extinction ratio ≥ 4.5 dB for extinction ratio < 4.5 dB | OMAouter -TDECQ |
-1.7 -1.6 |
dBm | ||
Transmitter and dispersion eye closure for PAM4 (TDECQ) | 3.4 | dB | |||
TECQ (PAM4) | 3.4 | dB | |||
TDECQ-10*log10(Ceq) ,each lane | 3.4 | dB | |||
RIN17.1 OMA | -136 | dB/Hz | |||
Average launch power of OFF transmitter | -20 | dBm | |||
Optical return loss tolerance | 17.1 | dB | |||
Transmitter Reflectance | -26 | dB | |||
Transmitter transition time | 17 | ps | |||
Transimitter over/under-shoot | 22 | % |
High Speed Optical Receiver Characteristics
Parameter | Symbol | Min. | Typical | Max. | Unit |
Signaling Speed Per Lane | 106.25 | Gbps | |||
Lane_1 Center Wavelength | λC1 | 1264.5 | 1277.5 | nm | |
Lane_2 Center Wavelength | λC2 | 1284.5 | 1297.5 | nm | |
Lane_3 Center Wavelength | λC3 | 1304.5 | 1317.5 | nm | |
Lane_4 Center Wavelength | λC4 | 1324.5 | 1337.5 | nm | |
Damage Threshold | 4.5 | dBm | |||
Average Receiver Power Per Lane | -7.3 | 3.5 | dBm | ||
Receive Power (Omaouter) Each Lane | RxOMA | 3.7 | dBm | ||
Difference In Receive Power Between Any Two Lanes(Omaouter) | 4.1 | dB | |||
Receiver Sensitivity (OMAouter), Each Lane | SenOMA | max(-4.6, SECQ-6.0) | dBm | ||
Stressed Eye Closure For PAM4 (SECQ), Lane Under Test | SECQ | 3.4 | dB | ||
Los Assert (Avg.) | LOSA | -15 | dBm | ||
Los De-Assert (Avg.) | LOSD | -10 | dBm | ||
Los Hysteresis | 0.5 | dB | |||
RSSI Accuracy | -2 | +2 | dB | ||
Receiver Reflectance | -26 | dB |
QSFP-DD Transceiver Electrical Pad Layout
Pin Descriptions
Pin | Logic | Symbol | Description | Plug Sequence4 | Notes | ||||||||
1 | GND | Ground | 1B | 1 | |||||||||
2 | CML-I | Tx2n | Transmitter Inverted Data Input | 3B | |||||||||
3 | CML-I | Tx2p | Transmitter Non- Inverted Data Input | 3B | |||||||||
4 | GND | Ground | 1B | 1 | |||||||||
5 | CML-I | Tx4n | Transmitter Inverted Data Input | 3B | |||||||||
6 | CML-I | Tx4p | Transmitter Non- Inverted Data Input | 3B | |||||||||
7 | GND | Ground | 1B | 1 | |||||||||
8 | LVTTL-I | ModSelL | Module Select | 3B | |||||||||
9 | LVTTL-I | ResetL | Module Reset | 3B | |||||||||
10 | VccRx | +3.3V Power Supply Receiver | 2B | 2 | |||||||||
11 | LVCMOS- I/O | SCL | 2-wire serial interface clock | 3B | |||||||||
12 | LVCMOS- I/O | SDA | 2-wire serial interface data | 3B | |||||||||
13 | GND | Ground | 1B | 1 | |||||||||
14 | CML-O | Rx3p | Receiver Non- | 3B | |||||||||
Inverted Data Output | |||||||||||||
15 | CML-O | Rx3n | Receiver Inverted Data Output | 3B | |||||||||
16 | GND | Ground | 1B | 1 | |||||||||
17 | CML-O | Rx1p | Receiver Non- | 3B | |||||||||
Inverted Data Output | |||||||||||||
18 | CML-O | Rx1n | Receiver Inverted | 3B | |||||||||
Data Output | |||||||||||||
19 | GND | Ground | 1B | 1 | |||||||||
20 | GND | Ground | 1B | 1 | |||||||||
21 | CML-O | Rx2n | Receiver Inverted | 3B | |||||||||
Data Output | |||||||||||||
22 | CML-O | Rx2p | Receiver Non- | 3B | |||||||||
Inverted Data Output | |||||||||||||
23 | GND | Ground | 1B | 1 | |||||||||
24 | CML-O | Rx4n | Receiver Inverted Data Output | 3B | |||||||||
25 | CML-O | Rx4p | Receiver Non- Inverted Data | 3B | |||||||||
Output | |||||||||||||
26 | GND | Ground | 1B | 1 | |||||||||
27 | LVTTL-O | ModPrsL | Module Present | 3B | |||||||||
28 | LVTTL-O | IntL | Interrupt | 3B | |||||||||
29 | VccTx | +3.3V Power supply | 2B | 2 | |||||||||
transmitter | |||||||||||||
30 | Vcc1 | +3.3V Power supply | 2B | 2 | |||||||||
31 | LVTTL-I | PLMode | Low Power Mode | 3B | |||||||||
32 | GND | Ground | 1B | 1 | |||||||||
33 | CML-I | Tx3p | Transmitter Non- | 3B | |||||||||
Inverted Data Input | |||||||||||||
34 | CML-I | Tx3n | Transmitter | 3B | |||||||||
Inverted Data Input | |||||||||||||
35 | GND | Ground | 1B | 1 | |||||||||
36 | CML-I | Tx1p | Transmitter Non- | 3B | |||||||||
Inverted Data Input | |||||||||||||
37 | CML-I | Tx1n | Transmitter | 3B | |||||||||
Inverted Data Input | |||||||||||||
38 | GND | Ground | 1B | 1 | |||||||||
39 | GND | Ground | 1A | 1 | |||||||||
40 | CML-I | Tx6n | Transmitter | 3A | |||||||||
Inverted Data Input | |||||||||||||
41 | CML-I | Tx6p | Transmitter Non- | 3A | |||||||||
Inverted Data Input | |||||||||||||
42 | GND | Ground | 1A | 1 | |||||||||
43 | CML-I | Tx8n | Transmitter | 3A | |||||||||
Inverted Data Input | |||||||||||||
44 | CML-I | Tx8p | Transmitter Non- | 3A | |||||||||
Inverted Data Input | |||||||||||||
45 | GND | Ground | 1A | 1 | |||||||||
46 | Reserved | For future use | 3A | 3 | |||||||||
47 | VS1 | Module Vendor | 3A | 3 | |||||||||
Specific 1 | |||||||||||||
48 | VccRx1 | 3.3V Power Supply | 2A | 2 | |||||||||
49 | VS2 | Module Vendor | 3A | 3 | |||||||||
Specific 2 | |||||||||||||
50 | VS3 | Module Vendor | 3A | 3 | |||||||||
Specific 3 | |||||||||||||
51 | GND | Ground | 1A | 1 | |||||||||
52 | CML-O | Rx7p | Receiver Non- | 3A | |||||||||
Inverted Data | |||||||||||||
Output | |||||||||||||
53 | CML-O | Rx7n | Receiver Inverted | 3A | |||||||||
Data Output | |||||||||||||
54 | GND | Ground | 1A | 1 | |||||||||
55 | CML-O | Rx5p | Receiver Non- | 3A | |||||||||
Inverted Data | |||||||||||||
Output | |||||||||||||
56 | CML-O | Rx5n | Receiver Inverted | 3A | |||||||||
Data Output | |||||||||||||
57 | GND | Ground | 1A | 1 | |||||||||
58 | GND | Ground | 1A | 1 | |||||||||
59 | CML-O | Rx6n | Receiver Inverted | 3A | |||||||||
Data Output | |||||||||||||
60 | CML-O | Rx6p | Receiver Non- | 3A | |||||||||
Inverted Data | |||||||||||||
Output | |||||||||||||
61 | GND | Ground | 1A | 1 | |||||||||
62 | CML-O | Rx8n | Receiver Inverted Data Output | 3A | |||||||||
63 | CML-O | Rx8p | Receiver Non- Inverted Data | 3A | |||||||||
Output | |||||||||||||
64 | GND | Ground | 1A | 1 | |||||||||
65 | NC | No Connect | 3A | 3 | |||||||||
66 | Reserved | For future use | 3A | 3 | |||||||||
67 | VccTx1 | 3.3V Power Supply | 2A | 2 | |||||||||
68 | Vcc2 | 3.3V Power Supply | 2A | 2 | |||||||||
69 | Reserved | For Future Use | 3A | 3 | |||||||||
70 | GND | Ground | 1A | 1 | |||||||||
71 | CML-I | Tx7p | Transmitter Non- | 3A | |||||||||
Inverted Data Input | |||||||||||||
72 | CML-I | Tx7n | Transmitter Inverted Data Input | 3A | |||||||||
73 | GND | Ground | 1A | 1 | |||||||||
74 | CML-I | Tx5p | Transmitter Non- Inverted Data Input | 3A | |||||||||
75 | CML-I | Tx5n | Transmitter Inverted Data Input | 3A | |||||||||
76 | GND | Ground | 1A | 1 | |||||||||
1: QSFP-DD uses common ground (GND) for all signals and supply (power). All are common within the QSFP -DD module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal-common ground plane. | |||||||||||||
2: VccRx, VccRx1, Vcc1, Vcc2, VccTx and VccTx1 shall be applied concurrently. VccRx, VccRx1, Vcc1, Vcc2, VccTx and VccTx1 may be internally connected within the module in any combination. The connector Vcc pins are each rated for a maximum current of 1000 mA. | |||||||||||||
3: All Vendor Specific, Reserved and No Connect pins may be terminated with 50 ohms to ground on the host. Pad 65 (No Connect) shall be left unconnected within the module. Vendor specific and Reserved pads shall have an impedance to GND that is greater than 10 k Ohms and less than 100 pF. | |||||||||||||
4: Plug Sequence specifies the mating sequence of the host connector and module. The sequence is 1A, 2A, 3A, 1B, 2B, 3B. Contact sequence A will make, then break contact with additional QSFP-DD pads. Sequence 1A, 1B will then occur simultaneously, followed by 2A, 2B, followed by 3A, 3B. |