AQD400C01310S50

425Gbps

SMF

500m

MPO12

0~+70℃

Yes

CMIS4.0

Storage   Temperature

Ts

-40

85

°C

Supply Voltage

Vcc

-0.5

3.6

V

Operating   Relative Humidity

RH

5

85

%

Operating Case   Temperature

Tc

0

70

°C

Power Supply   Voltage

Vcc

3.135

3.3

3.465

V

Power   Dissipation

PD

10

W

Electrical   Signal Rate Per Channel

26.5625

GBd

Optical Signal   Rate Per Channel

53.125

GBd

Receiver   Differential Data Output Load

100

Ohm

Transceiver Power   Consumption

8

10

W

Transceiver   Power Supply Total Current

2600

3200

mA

AC Coupling Internal   Capacitor

0.1

μF

TP0   to TP5

This channel includes   transmitter and receiver differential control impedance printed

circuit board   insertion loss and cable assembly insertion loss.

TP1   to TP4

All cable   assembly measurements are made between TP1 and TP4 as illustrated in

Figure 3.

TP0 to TP2   TP3 to TP5

A mated connector pair has been included in both the transmitter and receiver specifications defined in 802.3cd 136.9.3 and 136.9.4. The recommended maximum insertion loss from TP0 to TP2 or from TP3 to TP5 including the test fixture is provided in

802.3cd 136.9.3.2

TP2

Unless specified   otherwise, all transmitter measurements defined in 802.3cd 136.9.3 are

made at TP2 utilizing the test fixture specified   in Annex 136B.

TP3

Unless   specified otherwise, all receiver measurements and tests defined in 802.3cd

136.9.4 are   made at TP3 utilizing the test fixture specified in Annex 136B.

Signaling Rate Per Lane

TP1

26.5625

GBd

+/- 100 ppm

DC   Common-Mode Output Voltage

TP1

-350

2850

mV

Differential pk-pk Input   Voltage

Tolerance

TP1a

900

mV

Single-Ended   Voltage Tolerance Range

TP1a

-400

3300

mV

Differential Input Return   Loss (Min)

TP1

Equation

(83E-5)

dB

802.3bs

Differential to Common   Mode Inuput

Return Loss (Min)

TP1

Equation

(83E-6)

dB

802.3bs

Differential Termination Mismatch

TP1

10

%

Module Stressed Input Test

TP1a

Eye   Width

0.22

UI

Eye   Height

32

mV

Applied pk-pk Sinusoidal   Jitter

Table

120E-6

802.3bs

Signaling   Rate Per Lane(Range)

TP4a

26.5625   ± 100ppm

GBd

Common   Mode Voltage

TP4a

-0.35

2.85

V

Differential pk-pk Input   Voltage Tolerance

TP4

900

mV

Differential Input Return   Loss (Min)

TP4a

Equation(83E-2)

dB

Differential To Common Mode Input Return Loss (Min)

TP4a

Equation(83E-3)

dB

Differential Termination   Mismatch

TP4a

10

%

Transition time (20% to   80%)

TP4

9.5

ps

Signaling Speed Per Lane

106.25

Gbps

Modulation Format

PAM4

Center Wavelength

λ

1304.5

1311

1317.5

nm

Side-Mode Suppression   Ratio

SMSR

30

dB

Extinction Ratio

ER

3.5

dB

Average Launch Power

-2.4

4

dBm

OMA Per Lane

-0.2

4.2

dBm

Launch   Power In OMA-TDECQ

For Extinction Ratio ≥ 4.5 Db For Extinction   Ratio < 4.5 Db

-1.6

-1.5

dBm

Transmitter And Dispersion   Eye Closure For

PAM4 (TDECQ)

3.4

dB

TDECQ－10*Log10(Ceq)

3.4

dB

Tecq (Pam4)

3.4

dB

Rin17.1 Oma

-136

dB/Hz

Average Launch Power Of   OFF Transmitter

-15

dBm

Optical return loss   tolerance

21.4

dB

Transmitter Reflectance

-26

dB

Signaling Speed   Per Lane

106.25

Gbps

Center   Wavelength

λ

1304.5

1311

1317.5

nm

Damage   Threshold

5

dBm

Average   Receiver Power Per Lane

-5.9

4

dBm

Saturation   Receive Power (OMA) Per Lane

4.2

dBm

Unstressed Receiver Sensitivity (OMA) Per Lane For TECQ < 1.4 Db

For   1.4 Db≤ TECQ ≤ 3.4 Db

Sen

-4.4

TECQ-5.9

dBm

Los Assert   (Avg.)

LOSA

-15

dBm

Los De-Assert   (Avg.)

LOSD

-10

dBm

Los Hysteresis

0.5

dB

RSSI Accuracy

-2

+2

dB

Receiver   reflectance

-26

dB

1

GND

Ground

1B

1

2

CML-I

Tx2n

Transmitter Inverted Data Input

3B

3

CML-I

Tx2p

Transmitter Non- Inverted Data Input

3B

4

GND

Ground

1B

1

5

CML-I

Tx4n

Transmitter Inverted Data Input

3B

6

CML-I

Tx4p

Transmitter Non- Inverted Data Input

3B

7

GND

Ground

1B

1

8

LVTTL-I

ModSelL

Module Select

3B

9

LVTTL-I

ResetL

Module Reset

3B

10

VccRx

+3.3V Power Supply Receiver

2B

2

11

LVCMOS- I/O

SCL

2-wire serial interface clock

3B

12

LVCMOS- I/O

SDA

2-wire serial interface data

3B

13

GND

Ground

1B 1

14

CML-O

Rx3p

Receiver Non-

3B

Inverted Data Output

15

CML-O

Rx3n

Receiver Inverted Data Output

3B

16

GND

Ground

1B 1

17

CML-O

Rx1p

Receiver Non-

3B

Inverted Data Output

18

CML-O

Rx1n

Receiver Inverted Data Output

3B

19

GND

Ground

1B 1

20

GND

Ground

1B 1

21

CML-O

Rx2n

Receiver Inverted Data Output

3B

22

CML-O

Rx2p

Receiver Non-

3B

Inverted Data Output

23

GND

Ground

1B 1

24

CML-O

Rx4n

Receiver Inverted Data Output

3B

25

CML-O

Rx4p

Receiver Non- Inverted Data Output

3B

26

GND

Ground

1B 1

27

LVTTL-O

ModPrsL

Module Present

3B

28

LVTTL-O

IntL

Interrupt

3B

29

VccTx

+3.3V Power supply transmitter

2B 2

30

Vcc1

+3.3V Power supply

2B 2

31

LVTTL-I

PLMode

Low Power Mode

3B

32

GND

Ground

1B 1

33

CML-I

Tx3p

Transmitter Non- Inverted Data Input

3B

34

CML-I

Tx3n

Transmitter Inverted Data Input

3B

35

GND

Ground

1B 1

36

CML-I

Tx1p

Transmitter Non- Inverted Data Input

3B

37

CML-I

Tx1n

Transmitter Inverted Data Input

3B

38

GND

Ground

1B 1

39

GND

Ground

1A 1

40

CML-I

Tx6n

Transmitter Inverted Data Input

3A

41

CML-I

Tx6p

Transmitter Non-

3A

Inverted Data Input

42

GND

Ground

1A

1

43

CML-I

Tx8n

Transmitter

3A

Inverted Data Input

44

CML-I

Tx8p

Transmitter Non-

3A

Inverted Data Input

45

GND

Ground

1A

1

46

Reserved

For future use

3A

3

47

VS1

Module Vendor

3A

3

Specific 1

48

VccRx1

3.3V Power Supply

2A

2

49

VS2

Module Vendor

3A

3

Specific 2

50

VS3

Module Vendor

3A

3

Specific 3

51

GND

Ground

1A

1

52

CML-O

Rx7p

Receiver Non-

3A

Inverted Data

Output

53

CML-O

Rx7n

Receiver Inverted

3A

Data Output

54

GND

Ground

1A

1

55

CML-O

Rx5p

Receiver Non-

3A

Inverted Data

Output

56

CML-O

Rx5n

Receiver Inverted

3A

Data Output

57

GND

Ground

1A

1

58

GND

Ground

1A

1

59

CML-O

Rx6n

Receiver Inverted

3A

Data Output

60

CML-O

Rx6p

Receiver Non-

3A

Inverted Data

Output

61

GND

Ground

1A

1

62

CML-O

Rx8n

Receiver Inverted

3A

Data Output

63

CML-O

Rx8p

Receiver Non-

3A

Inverted Data

Output

64

GND

Ground

1A

1

65

NC

No Connect

3A

3

66

Reserved

For future use

3A

3

67

VccTx1

3.3V Power Supply

2A

2

68

Vcc2

3.3V Power Supply

2A

2

69

Reserved

For Future Use

3A

3

70

GND

Ground

1A

1

71

CML-I

Tx7p

Transmitter Non-

3A

Inverted Data Input

72

CML-I

Tx7n

Transmitter Inverted Data Input

3A

73

GND

Ground

1A

1

74

CML-I

Tx5p

Transmitter Non- Inverted Data Input

3A

75

CML-I

Tx5n

Transmitter Inverted Data Input

3A

76

GND

Ground

1A

1

2: VccRx, VccRx1, Vcc1, Vcc2, VccTx and VccTx1 shall be applied   concurrently. VccRx, VccRx1, Vcc1, Vcc2, VccTx and VccTx1 may be internally   connected within the module in any combination. The connector Vcc pins are   each rated for a

maximum   current of 1000 mA.

3: All Vendor Specific, Reserved and No Connect pins may be terminated   with 50 ohms to ground on the host. Pad 65 (No Connect) shall be left   unconnected within the module. Vendor specific and Reserved pads shall have   an impedance to

GND   that is greater than 10 k Ohms and less than 100 pF.

4: Plug   Sequence specifies the mating sequence of the host connector and module. The   sequence is 1A, 2A, 3A, 1B, 2B, 3B. Contact sequence A will make, then break   contact with additional QSFP-DD pads. Sequence 1A, 1B will then occur   simultaneously, followed by 2A, 2B, followed by 3A, 3B.