PRODUCTS > ACTIVE PRODUCTS > 100G > QSFP28 100G ZR
QSFP28 100G ZR
Accelight's 100Gbps QSFP28 transceiver module is designed for use in 100 Gigabit Ethernet links over 80km single mode fiber. The module has 4 independent electrical input/output channels operating up to 25.78Gbps per channel. This transceiver consists of transmitter/receiver units, with each operating on a set of 4 wavelengths on the ITU G.694.1 LAN-WDM grid near 1310nm. The transmitter path of the module incorporates 4-channel EMLs and 4-channel modulator driver. On the receiver path, a 1-channel SOA, 4- channel PD array, and 4-channel TIA array are used, along with NRZ re-timers.

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Product Details
  • Product Features
    Supports 103Gbps
    Single 3.3V power supply
    Power dissipation : 5.5W
    Up to 80km over SMF
    Commercial case temperature range of 0°C to 70°C
    Four 25Gbps EML LAN-WDM lasers on transmitter side
    Integrated Tap-PD,VOA,SOA and PIN TIA on receiver side
    4x25Gbps electrical interface
    Duplex LC receptacles
    I2C Interface with Integrated Digital Diagnostic Monitoring
    RoHS Compliant
  • Applications
    100G 80km applications with FEC on hostside
    100G Datacom & Telecom connections
  • Ordering information

    Part No.

    Data Rate

    Fiber

    Distance

    Interface

    Temp.

    DDMI

    AQP100CL4CHL080

    103Gbps

    SMF

    80km

    LC

    0~+70 

    Yes

     

  • Performance Specification

    Absolute Maximum Ratings

    Parameter

    Symbol

    Min.

    Max.

    Unit

    Storage Temperature

    Ts

    -40

    85

    °C

    Supply Voltage

    Vcc

    -0.5

    3.6

    V

    Relative Humidity

    RH

    5

    85

    %

    Recommended Operating Conditions

    Parameter

    Sym bol

    Min.

    Typical

    Max.

    Unit

    Storage Temperature

    Ts

    -40


    +85

    °C

    Operating Case   Temperature

    Tc

    0


    70

    °C

    Operating   Relative Humidity

    RH



    65

    %

    Power Supply Voltage

    Vcc

    3.135

    3.3

    3.465

    V

    Power Supply Noise




    25

    mVpp

    Power Dissipation

    PD



    5.5

    W

    Electrical Signal Rate Per   Channel



    25.78125


    GBd

    Optical Signal Rate Per   Channel



    25.78125


    GBd

    Receiver Differential Data Output Load


    90

    100

    110

    Ohm

    Fiber Length




    80

    Km

    100-1.png

    Figure 1: Transceiver Block Diagram

     

    100-2.png

    Figure 2: Application Reference Diagram

    Transmitter

    As shown in Figure 1, the transmitter path of the transceiver contains an 4x25Gbps CAUI-4 electrical input with equalization (EQ) block, integrated electrical multiplexer, EML driver, EML lasers and diagnostic monitor. The transmitter section uses a wavelength of L-WDM EML, it’s a class 1 laser compliant according to International Safety Standard IEC 60825.

    Receiver

    As shown in Figure 1, the optical receiver portion of the transceiver contains TAP-PD, VOA, SOA, four PDs, trans- impedance amplifiers (TIA), integrated de-multiplexer and CAUI-4 compliant electrical output blocks.

    High Speed Electrical Signal Interface

    The high speed signal lines are internally AC-coupled and the electrical inputs are internally terminated to 100 Ohms differential.All transmitter and receiver electrical channels are compliant to module XLAUI/CAUI specifications per IEEE 802.3ba.

    Control Signal Interface

    The module has the following low speed signals for control and status: ModSeL ModPrsL ResetL IntL/RxLOSL LPMode/TxDis. In addition, there is an industry standard two wire serial interface scaled for 3.3V LVCMOS. It is implemented as a slave device. Signal and timing characteristics are further defined in the Control Characteristics and Control Interface.

    Handling and Cleaning

    Exposure to current surges and overvoltage events can cause immediate damage to the transceiver module. Observe the precautions for normal operation of electrostatic discharge sensitive equipment; Attention shall also be paid to limiting transceiver module exposure to conditions beyond those specified in the absolute maximum ratings.

    Optical connectors include female connectors. These elements will be exposed as long as the cable or port plug is not inserted. At this time, always pay attention to protection.

    Each module is equipped with a port guard plug to protect the optical port. The protective plug shall always be in place whenever the optical fiber is not inserted. Before inserting the optical fiber, it is recommended to clean the end of the optical fiber connector to avoid contamination of the module optical port due to dirty connector. If contamination occurs, use standard LC port cleaning methods.

    General Electrical Characteristics

    Parameter

    Symbol

    Min.

    Typical

    Max.

    Unit

    Transceiver Power Consumption



    3.5

    5.5

    W

    Transceiver Power Supply Total Current



    1013

    1591

    mA

    AC Coupling Internal Capacitor



    0.1


    μF

    Reference Points

    The PMD block diagram is shown in Figure3. For purposes of system conformance, the PMD sublayer is standardized at the points described in this subclause. The optical transmit signal is defined at the output end of a single-mode fiber patch cord (TP2), between 2 m and 5 m in length. Unless specified otherwise, all transmitter measurements and tests defined in IEEE 802.3 88.8 are made at TP2. The optical receive signal is defined at the output of the fiber optic cabling (TP3) at the MDI (see IEEE 802.3 88.11.3). Unless specified otherwise, all receiver measurements and tests defined in IEEE 802.3 88.8 are made at TP3.

    100-3.png

    Figure 3: Block diagram for 100GBASE-LR4 and 100GBASE-ER4 transmit/receive paths

    100-4.png

    Figure 4: Host CAUI-4 compliance points TP1a, TP4a

    100-5.png

    Figure 5: IEEE 802.3 CAUI-4 compliance points TP1, TP4

    High Speed Electrical Input Characteristics

    Parameter

    Test

    Point

    Min.

    Typical

    Max.

    Unit

    Conditions

    Signaling Rate Per Lane

    TP1


    25.78125


    GBd

    +/- 100 ppm

    DC Common-Mode Output   Voltage

    TP1

    -350


    2850

    mV


    Differential pk-pk Input Voltage

    Tolerance

     

    TP1a

     

    900



     

    mV


    Single-Ended Voltage   Tolerance Range

     

    TP1a

     

    -400


     

    3300

     

    mV


     

    Differential Input Return   Loss (Min)

     

    TP1


    Equation   (83E-2)


     

    dB

    802.3ba

     

    Common To   Differential Mode Conversion Return Loss (Min)

     

    TP1


    Equation   (83E-3)


     

    dB

    802.3ba

     

    Differential Termination   Mismatch

     

    TP1



     

    10

     

    %


     

    Module Stressed Input Test



    83E.3.4.1




     

    Eye   Width

     

    TP1a


    0.46


     

    UI


     

    Eye Height

     

    TP1a


    95


     

    mV


     

    Applied pk-pk Sinusoidal   Jitter

     

    TP1a


    Table   88-13



    802.3ba

    High Speed Electrical Output Characteristics

    Parameter

    Test Point

    Min.

    Typical

    Max.

    Unit

    Signaling Rate Per   Lane(Range)

    TP4a


     

    25.78125±   100ppm


     

    GBd

    Common Mode Voltage

    TP4a

    -0.3


    2.8

    V

    Differential Pk-Pk Input   Voltage Tolerance

    TP4

    900



    mV

     

    Differential Input Return Loss (Min)

     

    TP4a


    Equation(83E-2)


     

    dB

    Differential To Common Mode Input Return Loss (Min)

     

    TP4a


    Equation(83E-3)


     

    dB

    Differential   Termination Mismatch

    TP4a


    10


    %

    Host   Stressed Input Test



    83E3.3.2



    Eye Width

    TP4


    0.57


    UI

    Eye Height

    TP4


    228


    mV

    Applied   pk-pk Sinusoidal Jitter

    TP4


    Table   88-13



    Optical Characteristics

    High Speed Optical Transmitter Characteristics

    Parameter

    Symbol

    Min.

    Typical

    Max.

    Unit

    Signaling Speed per Lane



    25.78125


    Gbps

    Modulation Format



    NRZ



    Data Rate Variation


    -100


    +100

    ppm

    Lane_0 Center Wavelength

    λC0

    1294.53

    1295.56

    1296.59

    nm

    Lane_1 Center Wavelength

    λC1

    1299.02

    1300.05

    1301.09

    nm

    Lane_2 Center Wavelength

    λC2

    1303.54

    1304.58

    1305.63

    nm

    Lane_3 Center Wavelength

    λC3

    1308.09

    1309.14

    1310.19

    nm

    Spectral Width (-20dB)

    Δλ



    1

    nm

    Total Average Output Power

    Po



    13

    dBm

    Average Launch Power per   Lane

    Peach

    2


    7

    dBm

    Optical Modulation   Amplitude(OMA), each lane

    Peach (OMA)

    3.7


    7.8

    dBm

    Average launch power of   OFF transmitter per lane

    Poff



    -30

    dBm

    Side-mode suppression   ratio

    SMSR

    30



    dB

    Transmitter dispersion   penalty ,each lane

    TDP



    3

    dB

    Difference in launch power   between any two lanes (OMA)




    3.6

    dB

    Optical Return Loss   Tolerance




    20

    dB

    Transmitter reflectance




    -26


    Extinction Ratio

    ER

    6

    8


    dB

    Transmitter eye mask   definition

    {X1, X2, X3, Y1, Y2, Y3}


    {0.25, 0.4, 0.45, 0.25,   0.28, 0.4}


    High Speed Optical Receiver Characteristics

    Parameter

    Symbol

    Min.

    Typical

    Max.

    Unit

    Signaling   Speed per Lane

    BRAVE


    25.78125


    Gbps

    Data   Rate Variation


    -100


    +100

    ppm

    Lane_0 Center Wavelength

    λC0

    1294.53

    1295.56

    1296.59

    nm

    Lane_1 Center Wavelength

    λC1

    1299.02

    1300.05

    1301.09

    nm

    Lane_2 Center Wavelength

    λC2

    1303.54

    1304.58

    1305.63

    nm

    Lane_3   Center Wavelength

    λC3

    1308.09

    1309.14

    1310.19

    nm

    Average Receive Power per   Lane

    Rx_pow

    -31


    4.5

    dBm

    Receiver overload per Lane

    Psat

    4.5



    dBm

    Damage threshold per   lane(min)

    Pdamage



    5.5

    dBm

    Receive sensitivity   average per lane

    Rx_sens



    -29

    dBm

    Stressed Receiver   Sensitivity per Lane

    RXSRS



    -25.1

    dBm

    Receiver Reflectance

    ORL



    -26

    dB

    LOS Assert

    LOSA

    -40



    dBm

    LOS De-Assert

    LOSD



    -31.5

    dBm

    LOS Hysteresis


    0.5



    dB

    QSFP28 Transceiver Electrical Pad Layout

    100-6.png

    Pin Descriptions

    Pin

    Logic

    Symbol

    Description

    Plug Sequence

    Notes

    1


    GND

    Ground

    1

    1

    2

    CML-I

    Tx2n

    Transmitter   Inverted Data Input

    3


    3

    CML-I

    Tx2p

    Transmitter Non-Inverted Data Input

    3


    4


    GND

    Ground

    1

    1

    5

    CML-I

    Tx4n

    Transmitter   Inverted Data Input

    3


    6

    CML-I

    Tx4p

    Transmitter Non-Inverted Data Input

    3


    7


    GND

    Ground

    1

    1

    8

    LVTTL-I

    ModSelL

    Module   Select

    3


    9

    LVTTL-I

    ResetL

    Module   Reset

    3


    10


    VccRx

    +3.3V   Power Supply Receiver

    2

    2

    11

    LVCMOS-

    I/O

    SCL

    Two-wire serial interface clock

    3


    12

    LVCMOS-

    I/O

    SDA

    Two-wire serial interface data

    3


    13


    GND

    Ground

    1

    1

    14

    CML-O

    Rx3p

    Receiver Non-Inverted Data Output

    3



    15

    CML-O

    Rx3n

    Receiver Inverted Data Output

    3



    16


    GND

    Ground

    1


    1

    17

    CML-O

    Rx1p

    Receiver Non-Inverted Data Output

    3



    18

    CML-O

    Rx1n

    Receiver   Inverted Data Output

    3



    19


    GND

    Ground

    1


    1

    20


    GND

    Ground

    1


    1

    21

    CML-O

    Rx2n

    Receiver Inverted Data Output

    3



    22

    CML-O

    Rx2p

    Receiver Non-Inverted Data Output

    3



    23


    GND

    Ground

    1


    1

    24

    CML-O

    Rx4n

    Receiver Inverted Data Output

    3



    25

    CML-O

    Rx4p

    eceiver   Non-Inverted Data Output

    3



    26


    GND

    Ground

    1

    1


    27

    LVTTL-O

    ModPrsL

    Module Present

    3



     

    28

     

    LVTTL-O

    IntL/ RxLOSL

    Interrupt. Optionally configurable as   RxLOSL via the management

     

    3






    interface (SFF-8636).




    29


    VccTx

    +3.3V Power supply transmitter

    2


    2

    30


    Vcc1

    +3.3V Power supply

    2

    2


     

    31

     

    LVTTL-I

    LPMode/ TxDis

    Low Power Mode. Optionally configurable   as TxDis via the

     

    3






    management interface   (SFF-8636).




    32


    GND

    Ground

    1


    1

    33

    CML-I

    Tx3p

    Transmitter Non-Inverted Data input

    3



    34

    CML-I

    Tx3n

    Transmitter Inverted Data Input

    3



    35


    GND

    Ground

    1


    1

    36

    CML-I

    Tx1p

    Transmitter   Non-Inverted Data

    3






    Input




    37

    CML-I

    Tx1n

    Transmitter Inverted Data Input

    3



    38


    GND

    Ground

    1


    1

    1: GND is the symbol for   signal and supply (power) common for the module. All are common within the   module and all module voltages are referenced to this potential unless   otherwise noted. Connect them

    directly to the host board   signal-common ground plane.

    2: VccRx, Vcc1 and VccTx   are the receiving and transmission power suppliers and applied

    concurrently. VccRx, Vcc1   and VccTx are internally connected within the module in any combination. Vcc   contacts in SFF-

    8662   and SFF-8672 each have a steady state current rating of 1A.

    100-7.png

  • Mechanical Specifications

    100-8.png

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