PRODUCTS > ACTIVE PRODUCTS > 400G > QSFP56-DD 400G DR4
QSFP56-DD 400G DR4
Accelight's QSFP-DD 4*100Gbps transceiver module is designed for optical communication applications in 400 Gigabit Ethernet links over 500m single mode fiber. This product converts 8 channels of 50Gbps (PAM4) electrical input data to 4 channels of 100Gbps (PAM4) parallel optical signals. Reversely, on the receiver side, 4 channels of parallel optical signals of 100Gbps (PAM4) converts to 8 channels of 50Gbps (PAM4) electrical output data. The central wavelengths of 4 parallel channels are 1310nm, and per channel operating at 100Gbps. The electrical interface of the module is compliant with the 400GAUI-8 interface as defined by IEEE 802.3bs, and the form factor, optical/electrical connection and digital diagnostic interface compliant with QSFP-DD MSA.

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Product Details
  • Product Features
    Supports 425Gbps
    Single 3.3V Power Supply
    Power dissipation < 10W
    Up to 500m over SMF
    RoHS compliant
    QSFP-DD MSA Compliant
    8x53.125Gbps (PAM4) electrical interface
    MPO-12 connector
    Commercial case temperature range of 0°C to 70°
    PIN and TIA array on the receiver side
    I2C interface with integrated Digital Diagnostic Monitoring
  • Applications
    4 x 100G-DR application
    Infiniband interconnects
    Data center
  • Ordering information

    Part No.

    Data Rate

    Fiber

    Distance

    Interface

    Temp.

    DDMI

    CMIS

    AQD400C01310S50

    425Gbps

    SMF

    500m

    MPO12

    0~+70

    Yes

    CMIS4.0


  • Performance Specification

    Absolute Maximum Ratings

    Parameter

    Symbol

    Min.

    Max.

    Unit

    Storage   Temperature

    Ts

    -40

    85

    °C

    Supply Voltage

    Vcc

    -0.5

    3.6

    V

    Operating   Relative Humidity

    RH

    5

    85

    %

    Recommended Operating Conditions

    Parameter

    Symbol

    Min.

    Typical

    Max.

    Unit

    Operating Case   Temperature

    Tc

    0


    70

    °C

    Power Supply   Voltage

    Vcc

    3.135

    3.3

    3.465

    V

    Power   Dissipation

    PD



    10

    W

    Electrical   Signal Rate Per Channel



    26.5625


    GBd

    Optical Signal   Rate Per Channel



    53.125


    GBd

    Receiver   Differential Data Output Load


    100



    Ohm

    400-1.png

    Figure 1: Transceiver Block Diagram

     

    400-2.png

    Figure 2: Application Reference Diagram

    Transmitter

    As shown in Figure 1, the transmitter path of the transceiver contains an 8x50Gbps 400GAUI-8 electrical input with equalization (EQ) block, integrated electrical multiplexer, EML driver, EML lasers and diagnostic monitor. The integrated electrical multiplexer converts 8 channels of 50 Gbps (PAM4) electrical input data to 4 channels of 100Gbps (PAM4) parallel optical signals.

    Receiver

    As shown in Figure 1, the  receiver  path  of  the  transceiver  contains  four  PIN  photodiodes, trans- impedance amplifiers (TIA), integrated de-multiplexer and 8x50G 400GAUI-8 compliant electrical output blocks. The integrated de-multiplexer converts 4 channels of 100Gbps (PAM4) parallel optical signals to 8 channels of 50Gbps (PAM4) electrical output data.

    High Speed Electrical Signal Interface

    The interface between QSFP-DD module and ASIC/SerDes is shown in Figure 2. The high speed signal lines are internally AC-coupled and the electrical inputs are internally terminated to 100 Ohms differential. All transmitter and receiver electrical channels are compliant to module 400GAUI-8 specifications per IEEE 802.3bs.

    Control Signal Interface

    The control signal interface is compliant with QSFP-DD MSA. The following pin is provided to control module or display the module status: ModPrsL, IntL/RxLOS, ResetL, LPMode/TxDis. In addition, there is an industry standard two wire serial interface scaled for 3.3V LVTTL. The definition of control signal interface and the registers of the serial interface memory are defined in the Control Interface & Memory Map section.

    Handling and Cleaning

    Exposure to current surges and overvoltage events can cause immediate damage to the transceiver module. Observe the precautions for normal operation of electrostatic discharge sensitive equipment; Attention shall also be paid to limiting transceiver module exposure to conditions beyond those specified in the absolute maximum ratings.

    Optical connectors include female connectors. These elements will be exposed as long as the cable or port plug is not inserted. At this time, always pay attention to protection.

    Each module is equipped with a port guard plug to protect the optical port. The protective plug shall always be in place whenever the optical fiber is not inserted. Before inserting the optical fiber, it is recommended to clean the end of the optical fiber connector to avoid contamination of the module optical port due to dirty connector. If contamination occurs, use standard MPO port cleaning methods.

    General Electrical Characteristics

    Parameter

    Symbol

    Min.

    Typical

    Max.

    Unit

    Transceiver Power   Consumption



    8

    10

    W

    Transceiver   Power Supply Total Current



    2600

    3200

    mA

    AC Coupling Internal   Capacitor



    0.1


    μF

    Reference Points

    Test Point

    Description

     

    TP0   to TP5

    This channel includes   transmitter and receiver differential control impedance printed

    circuit board   insertion loss and cable assembly insertion loss.

     

    TP1   to TP4

    All cable   assembly measurements are made between TP1 and TP4 as illustrated in

    Figure 3.

     

    TP0 to TP2   TP3 to TP5

    A mated connector pair has been included in both the transmitter and receiver specifications defined in 802.3cd 136.9.3 and 136.9.4. The recommended maximum insertion loss from TP0 to TP2 or from TP3 to TP5 including the test fixture is provided in

    802.3cd 136.9.3.2

     

    TP2

    Unless specified   otherwise, all transmitter measurements defined in 802.3cd 136.9.3 are

    made at TP2 utilizing the test fixture specified   in Annex 136B.

     

    TP3

    Unless   specified otherwise, all receiver measurements and tests defined in 802.3cd

    136.9.4 are   made at TP3 utilizing the test fixture specified in Annex 136B.

     400-3.jpg

    Figure 3: IEEE 802.3cd 50GBASE-CR, 100GBASE-CR2 or 200GBASE-CR4 link

    400-4.png

    Figure 4: IEEE 802.3bs 400GAUI-8 compliance points TP1a, TP4a

     

    400-5.png

    Figure 5: IEEE 802.3bs 400GAUI-8 compliance points TP1, TP4

    High Speed Electrical Input Characteristics

     

    Parameter

    Test

    Point

    Min.

    Typical

    Max.

    Unit

    Conditions

    Signaling Rate Per Lane

    TP1


    26.5625


    GBd

    +/- 100 ppm

    DC   Common-Mode Output Voltage

    TP1

    -350


    2850

    mV


    Differential pk-pk Input   Voltage

    Tolerance

    TP1a

    900



    mV


    Single-Ended   Voltage Tolerance Range

    TP1a

    -400


    3300

    mV


    Differential Input Return   Loss (Min)

    TP1


    Equation

    (83E-5)


    dB

    802.3bs

    Differential to Common   Mode Inuput

    Return Loss (Min)

    TP1


    Equation

    (83E-6)


    dB

    802.3bs

    Differential Termination Mismatch

    TP1



    10

    %


    Module Stressed Input Test

    TP1a






    Eye   Width



    0.22


    UI


    Eye   Height



    32


    mV


    Applied pk-pk Sinusoidal   Jitter



    Table

    120E-6



    802.3bs

    High Speed Electrical Output Characteristics

     

    ParamPareter

    Test Point

    Min.

    Typical

    Max.

    Unit

    Signaling   Rate Per Lane(Range)

    TP4a


    26.5625   ± 100ppm


    GBd

    Common   Mode Voltage

    TP4a

    -0.35


    2.85

    V

    Differential pk-pk Input   Voltage Tolerance

    TP4



    900

    mV

     

    Differential Input Return   Loss (Min)

     

    TP4a


    Equation(83E-2)


     

    dB

    Differential To Common Mode Input Return Loss (Min)

     

    TP4a


    Equation(83E-3)


     

    dB

    Differential Termination   Mismatch

    TP4a



    10

    %

    Transition time (20% to   80%)

    TP4

    9.5



    ps

    Optical Characteristics

    High Speed Optical Transmitter Characteristics

    Parameter

    Symbol

    Min.

    Typical

    Max.

    Unit

    Signaling Speed Per Lane



    106.25


    Gbps

    Modulation Format



    PAM4



    Center Wavelength

    λ

    1304.5

    1311

    1317.5

    nm

    Side-Mode Suppression   Ratio

    SMSR

    30



    dB

    Extinction Ratio

    ER

    3.5



    dB

    Average Launch Power


    -2.4


    4

    dBm

    OMA Per Lane


    -0.2


    4.2

    dBm

    Launch   Power In OMA-TDECQ

    For Extinction Ratio 4.5 Db For Extinction   Ratio < 4.5 Db


     

    -1.6

    -1.5



     

    dBm

    Transmitter And Dispersion   Eye Closure For

    PAM4 (TDECQ)




     

    3.4

     

    dB

    TDECQ10*Log10(Ceq)




    3.4

    dB

    Tecq (Pam4)




    3.4

    dB

    Rin17.1 Oma




    -136

    dB/Hz

    Average Launch Power Of   OFF Transmitter




    -15

    dBm

    Optical return loss   tolerance




    21.4

    dB

    Transmitter Reflectance




    -26

    dB

    High Speed Optical Receiver Characteristics

    Parameter

    Symbol

    Min.

    Typical

    Max.

    Unit

    Signaling Speed   Per Lane



    106.25


    Gbps

    Center   Wavelength

    λ

    1304.5

    1311

    1317.5

    nm

    Damage   Threshold


    5



    dBm

    Average   Receiver Power Per Lane


    -5.9


    4

    dBm

    Saturation   Receive Power (OMA) Per Lane




    4.2

    dBm

    Unstressed Receiver Sensitivity (OMA) Per Lane For TECQ < 1.4 Db

    For   1.4 DbTECQ 3.4 Db

     

    Sen



     

    -4.4

    TECQ-5.9

     

    dBm

    Los Assert   (Avg.)

    LOSA

    -15



    dBm

    Los De-Assert   (Avg.)

    LOSD



    -10

    dBm

    Los Hysteresis


    0.5



    dB

    RSSI Accuracy


    -2


    +2

    dB

    Receiver   reflectance




    -26

    dB

    QSFP-DD Transceiver Electrical Pad Layout

     400-4.jpg400-5.jpg

    Pin Descriptions

    Pin

    Logic

    Symbol

    Description

    Plug Sequence4

    Notes

    1


    GND

    Ground

    1B

    1

    2

    CML-I

    Tx2n

    Transmitter Inverted Data Input

    3B


    3

    CML-I

    Tx2p

    Transmitter Non- Inverted Data Input

    3B


    4


    GND

    Ground

    1B

    1

    5

    CML-I

    Tx4n

    Transmitter Inverted Data Input

    3B


    6

    CML-I

    Tx4p

    Transmitter Non- Inverted Data Input

    3B


    7


    GND

    Ground

    1B

    1

    8

    LVTTL-I

    ModSelL

    Module Select

    3B


    9

    LVTTL-I

    ResetL

    Module Reset

    3B


    10


    VccRx

    +3.3V Power Supply Receiver

    2B

    2

    11

    LVCMOS- I/O

    SCL

    2-wire serial interface clock

    3B


    12

    LVCMOS- I/O

    SDA

    2-wire serial interface data

    3B


    13


    GND

    Ground

    1B 1


    14

    CML-O

    Rx3p

    Receiver Non-

    3B


    Inverted Data Output

    15

    CML-O

    Rx3n

    Receiver Inverted Data Output

    3B


    16


    GND

    Ground

    1B 1


    17

    CML-O

    Rx1p

    Receiver Non-

    3B


    Inverted Data Output

    18

    CML-O

    Rx1n

    Receiver Inverted Data Output

    3B


    19


    GND

    Ground

    1B 1


    20


    GND

    Ground

    1B 1


    21

    CML-O

    Rx2n

    Receiver Inverted Data Output

    3B


    22

    CML-O

    Rx2p

    Receiver Non-

    3B


    Inverted Data Output

    23


    GND

    Ground

    1B 1


    24

    CML-O

    Rx4n

    Receiver Inverted Data Output

    3B


    25

    CML-O

    Rx4p

    Receiver Non- Inverted Data Output

    3B


    26


    GND

    Ground

    1B 1


    27

    LVTTL-O

    ModPrsL

    Module Present

    3B


    28

    LVTTL-O

    IntL

    Interrupt

    3B


    29


    VccTx

    +3.3V Power supply transmitter

    2B 2


    30


    Vcc1

    +3.3V Power supply

    2B 2


    31

    LVTTL-I

    PLMode

    Low Power Mode

    3B


    32


    GND

    Ground

    1B 1


    33

    CML-I

    Tx3p

    Transmitter Non- Inverted Data Input

    3B


    34

    CML-I

    Tx3n

    Transmitter Inverted Data Input

    3B


    35


    GND

    Ground

    1B 1


    36

    CML-I

    Tx1p

    Transmitter Non- Inverted Data Input

    3B


    37

    CML-I

    Tx1n

    Transmitter Inverted Data Input

    3B


    38


    GND

    Ground

    1B 1


    39


    GND

    Ground

    1A 1


    40

    CML-I

    Tx6n

    Transmitter Inverted Data Input

    3A


    41

    CML-I

    Tx6p

    Transmitter Non-

    3A





    Inverted Data Input



    42


    GND

    Ground

    1A

    1

    43

    CML-I

    Tx8n

    Transmitter

    3A





    Inverted Data Input



    44

    CML-I

    Tx8p

    Transmitter Non-

    3A





    Inverted Data Input



    45


    GND

    Ground

    1A

    1

    46


    Reserved

    For future use

    3A

    3

    47


    VS1

    Module Vendor

    3A

    3




    Specific 1



    48


    VccRx1

    3.3V Power Supply

    2A

    2

    49


    VS2

    Module Vendor

    3A

    3




    Specific 2



    50


    VS3

    Module Vendor

    3A

    3




    Specific 3



    51


    GND

    Ground

    1A

    1

    52

    CML-O

    Rx7p

    Receiver Non-

    3A





    Inverted Data






    Output



    53

    CML-O

    Rx7n

    Receiver Inverted

    3A





    Data Output



    54


    GND

    Ground

    1A

    1

    55

    CML-O

    Rx5p

    Receiver Non-

    3A





    Inverted Data






    Output



    56

    CML-O

    Rx5n

    Receiver Inverted

    3A





    Data Output



    57


    GND

    Ground

    1A

    1

    58


    GND

    Ground

    1A

    1

    59

    CML-O

    Rx6n

    Receiver Inverted

    3A





    Data Output



    60

    CML-O

    Rx6p

    Receiver Non-

    3A





    Inverted Data






    Output



    61


    GND

    Ground

    1A

    1

    62

    CML-O

    Rx8n

    Receiver Inverted

    3A





    Data Output



    63

    CML-O

    Rx8p

    Receiver Non-

    3A





    Inverted Data






    Output



    64


    GND

    Ground

    1A

    1

    65


    NC

    No Connect

    3A

    3

    66


    Reserved

    For future use

    3A

    3

    67


    VccTx1

    3.3V Power Supply

    2A

    2

    68


    Vcc2

    3.3V Power Supply

    2A

    2

    69


    Reserved

    For Future Use

    3A

    3

    70


    GND

    Ground

    1A

    1

    71

    CML-I

    Tx7p

    Transmitter Non-

    3A





    Inverted Data Input



    72

    CML-I

    Tx7n

    Transmitter Inverted Data Input

    3A


    73


    GND

    Ground

    1A

    1

    74

    CML-I

    Tx5p

    Transmitter Non- Inverted Data Input

    3A


    75

    CML-I

    Tx5n

    Transmitter Inverted Data Input

    3A


    76


    GND

    Ground

    1A

    1


    1: QSFP-DD uses common ground (GND) for all signals and supply (power). All are common within the QSFP -DD module   and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board

    signal-common ground plane.


    2: VccRx, VccRx1, Vcc1, Vcc2, VccTx and VccTx1 shall be applied   concurrently. VccRx, VccRx1, Vcc1, Vcc2, VccTx and VccTx1 may be internally   connected within the module in any combination. The connector Vcc pins are   each rated for a

    maximum   current of 1000 mA.


    3: All Vendor Specific, Reserved and No Connect pins may be terminated   with 50 ohms to ground on the host. Pad 65 (No Connect) shall be left   unconnected within the module. Vendor specific and Reserved pads shall have   an impedance to

    GND   that is greater than 10 k Ohms and less than 100 pF.


    4: Plug   Sequence specifies the mating sequence of the host connector and module. The   sequence is 1A, 2A, 3A, 1B, 2B, 3B. Contact sequence A will make, then break   contact with additional QSFP-DD pads. Sequence 1A, 1B will then occur   simultaneously, followed by 2A, 2B, followed by 3A, 3B.


    400-6.jpg

  • Mechanical Specifications

    400-7.jpg

    400-8.png400-9.jpg

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