PRODUCTS > ACTIVE PRODUCTS > 400G > QSFP56-DD 400G ZR
QSFP56-DD 400G ZR
Accelight’s QSFP-DD 400Gbps transceiver module is designed for optical communication applications in 400 Gigabit Ethernet links over 120km single mode fiber. This product converts 8 channels of 50 Gbps (PAM4) electrical input data to single channel of 400Gbps (DP-16QAM) coherent optical signals. Reversely, on the receiver side, 400Gbps (DP-16QAM) coherent optical signals is converted to 8 channels of 50Gbps (PAM4) electrical output data. The electrical interface of the module is compliant with the 400GAUI-8 interface as defined by IEEE 802.3bs, and the form factor, optical/electrical connection and digital diagnostic interface compliant with QSFP-DD MSA.

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Product Details
  • Product Features
    Supports 425Gbps
    Single 3.3V Power Supply
    Power dissipation < 19W
    Up to 120km over SMF with EDFA
    RoHS compliant
    QSFP-DD MSA Compliant
    8x53.125G(PAM4) electrical interface
    Duplex LC connector
    Commercial case temperature range of 0°C to 70°
    I2C interface with integrated Digital Diagnostic Monitoring
  • Applications
    400G ZR Application
    Data center
    DWDM networks
  • Standards
  • Ordering information

    Part No.

    Data Rate

    Fiber

    Distance

    Interface

    Temp.

    DDMI

    AQD400CDxxxx120

    400Gbps

    SMF

    120km

    LC

    0~+70 

    Yes

    Note: XXXX means DWDM wavelength.


  • Performance Specifications

    Absolute Maximum Ratings

    Parameter

    Symbol

    Min.

    Max.

    Unit

    Storage Temperature

    Ts

    -40

    85

    °C

    Supply Voltage

    Vcc

    -0.5

    3.6

    V

    Damage threshold

    Rxdmg

    5.5


    dBm

    Recommended Operating Conditions

    Parameter

    Symbol

    Min.

    Typical

    Max.

    Unit

    Operating Case Temperature

    Tc

    0


    70

    C

    Power supply voltage

    Vcc

    3.135

    3.3

    3.465

    V

    Power supply noise




    66

    mVpp

    Power Dissipation

    PD



    19

    w

    Electrical signal rate per   channel



    26.5625


    GBd

    Optical signal rate per   channel



    59.84375


    GBd

    Receiver differential data Output load


    100



    Ohm

    Fiber length




    120

    km

    image.png

    Figure 1: Transceiver Block Diagram

    image.png

    Figure 2: Application Reference Diagram

    Transmitter

    As shown in Figure 1, the transmitter path of the transceiver contains an 8x50Gbps 400GAUI-8 electrical input with equalization (EQ) block, integrated electrical multiplexer, iTLA, MZM and diagnostic monitor. The integrated electrical multiplexer converts 8 channels of 50 Gbps (PAM4) electrical input data to single channel of 400Gbps (DP-16QAM) optical signals.

     

    Receiver

    As shown in Figure 1, the receiver path of the transceiver contains eight PIN photodiodes, four trans- impedance amplifiers (TIA), integrated de-multiplexer and 8x50G 400GAUI-8 compliant electrical output blocks. The integrated de-multiplexer converts single channel of 400Gbps (DP-16QAM) optical signals to 8 channels of 50Gbps (PAM4) electrical output data.

     

     

    High Speed Electrical Signal Interface

    The interface between QSFP-DD module and ASIC/SerDes is shown in Figure 2. The high speed signal lines are internally AC-coupled and the electrical inputs are internally terminated to 100 Ohms differential. All transmitter and receiver electrical channels are compliant to module 400GAUI-8 specifications per IEEE 802.3bs.

     

    Control Signal Interface

    The control signal interface compliant with QSFP-DD MSA. The following pin are provided to control module or display the module status: ModPrsL, IntL/RxLOS, ResetL, LPMode/TxDis. In addition, there is an industry standard two wire serial interface scaled for 3.3 volt LVTTL. The definition of control signal interface and the registers of the serial interface memory are defined in the Control Interface & Memory Map section.

     

    Handling and Cleaning

    Exposure to current surges and overvoltage events can cause immediate damage to the transceiver module. Observe the precautions for normal operation of electrostatic discharge sensitive equipment; Attention shall also be paid to limiting transceiver module exposure to conditions beyond those specified in the absolute maximum ratings.

    Optical connectors include female connectors. These elements will be exposed as long as the cable or port plug is not inserted. At this time, always pay attention to protection.

    Optical connectors include female connectors. These elements will be exposed as long as the cable or port plug is not inserted. At this time, always pay attention to protection.


    General Electrical Characteristics

    Parameter

    Symbol

    Min.

    Typical

    Max.

    Unit

    Transceiver Power Consumption



    18

    19

    w

    Transceiver Power Supply Total Current



    5450

    6060

    mA

    AC Coupling Internal Capacitor



    0.1


    uF


    Reference Points


    Reference Points

    Reference Points

    Reference Points

    Reference Points

    Reference Points

    Reference Points

    Reference Points

    Reference Points

    TP3 to TP5

    A mated connector pair   has been included in both the transmitter and receiver specifications defined   in 802.3cd 136.9.3 and 136.9.4. The recommended maximum insertion loss from   TP0 to TP2 or from TP3 to TP5 including the test fixture is provided

    in 802.3cd   136.9.3.2

    TP2

    Unless specified otherwise, all   transmitter measurements defined in 802.3cd 136.9.3 are made at TP2 utilizing   the test fixture specified in Annex 136B.

    TP3

    Unless specified otherwise, all receiver   measurements and tests defined in 802.3cd

    136.9.4 are made at TP3   utilizing the test fixture specified in Annex 136B


    image.png

    Figure 3: IEEE 802.3cd 50GBASE-CR, 100GBASE-CR2 or 200GBASE-CR4 link

    image.png

    image.png

    Figure 5: IEEE 802.3bs 400GAUI-8 compliance points TP1, TP4

    High Speed Electrical Input Characteristics


    Parameter

    Test

    Point

    Min.

    Typical

    Max.

    Unit

    Conditions

    Signaling rate, per lane(PAM4 encoded)

    TP1


    26.5625


    GBd


    Differential Peak-Peak   Input Voltage

    Tolerance

    TP1a

    900



    mV


    Differential Input Return   Loss (Min)

    TP1


    Equation (83E-5)


    dB


    Differential To Common   Mode Input

    Return Loss (Min)

    TP1


    Equation   (83E-6)


    dB


    Differential Termination   Mismatch

    TP1



    10

    %


    Single-Ended Voltage   Tolerance Range

    TP1a

    -0.4


    3.3

    V


    DC Common-Mode Output   Voltage

    TP1

    -350


    2850

    mV


    Eye   Width



    0.22


    UI


    Eye Height



    32


    mV



    High Speed Electrical Output Characteristics

    Parameter

    Test Point

    Min.

    Typical

    Max.

    Unit

    Signaling rate, per lane

    TP4a


    26.5625


    GBd

    Differential Peak-Peak Input Voltage

    Tolerance

    TP4

    900



    mV

    Differential Input Return   Loss (Min)

    TP4a


    Equation (83E-5)


    dB

     

    Differential To   Common Mode Input Return Loss (Min)

     

    TP4a


    Equation (83E-6)


     

    dB

    Differential Termination   Mismatch

     

    TP4a



     

    10

     

    %

    Common-Mode Voltage

    TP4a

    -350


    2850

    mV

    Transition time(20%-80%)

    TP4

    9.5



    ps

    Optical Characteristics


    High Speed Optical Transmitter Characteristics


    Parameter

    Sym bol

    Min.

    Typical

    Max.

    Unit

    Signaling Speed



    59.84375±20ppm


    GBd

    Modulation   format



    DP-16QAM



    Channel frequency

    λ

    191.3


    196.1

    THz

    Channel Spacing



    100(75)


    GHz

    Wavelength   Accuracy


    -1.8


    1.8

    GHz

    Tx   Spectral Excursion




    32

    GHz

    Average launch power


    -10


    -6

    dBm

    Average launch power


    -9


    0

    dBm

    Output   power with Tx disabled




    -20

    dBm

    Output power during wavelength

    switching




    -20

    dBm

    In   band OSNR


    34



    dB/0.1nm

    Out   of band OSNR


    23



    dB/0.1nm

    Transmitter   Reflectance




    -20

    dB

    Transmitter   back reflectance tolerance




    -24

    dB

    Transmitter   polarization dependent

    power




    1.5

    dBm

    X-Y Skew




    5

    ps

    DC   I-Q offset(mean per polarization)




    -26

    dB

    I-Q   instantaneous offset




    -20

    dB

    Mean   I-Q amplitude imbalance




    1

    dB

    I-Q   phase imbalance


    -5


    5

    degrees

    I-Q   Skew(per polarization)




    0.75

    ps

    Laser   RIN(0.2GHz≤f≤10GHz Avg)




    -145

    dB/Hz

    Laser   RIN(0.2GHz≤f≤10GHz Peak)




    -140

    dB/Hz

    Transmitter   laser disable time




    100

    ms

    Transmitter   turn-up time from warm start




    180

    s

    Transmitter   turn-up time from cold start




    200

    s

    Transmitter   wavelength switching time




    180

    s

    Output power monitor Accuracy


    -2


    2

    dB

    High Speed Optical Receiver Characteristics

    Optical Characteristics @TP3 Test Point (DWDM amplified)

    Parameter

    Symbol

    Min.

    Typical

    Max.

    Unit

    Signaling Speed



    59.84375±20ppm


    GBd

    Channel frequency

    λ

    191.3


    196.1

    THz

    Frequency offset between received


    -3.6


    3.6

    GHz

    carrier

    and LO






    Input power range


    -12


    13

    dBm

    Input sensitivity

    Sen

    -12



    dBm

    OSNR Tolerance




    26

    dB/0.1nm

    Optical return loss


    20



    dB

    CD Tolerance


    2400



    ps/nm

    Optical path OSNR penalty tolerance




    0.5

    dB

    PMD tolerance


    10



    ps

    Peak PDL tolerance


    3.5



    dB

    Tolerance to change in SOP


    50



    Krad/s

    Optical input power transient tolerance


    -2


    2

    dB

    Receiver turn-up time from warm start




    10

    s

    Receiver turn-up time from cold start




    200

    s

    Intput power monitor Accuracy


    -4


    4

    dB

    Optical Rx_LOS Assert Threshold

    LOSA

    -20



    dBm

    Optical Rx_LOS Deassert Threshold

    LOSD



    -15

    dBm

    Optical Rx_LOS Hysteresis


    1


    2.5

    dBm

    Optical Characteristics @TP3 Test Point (single wavelength unamplified)

    Parameter

    Symbol

    Min.

    Typical

    Max.

    Unit

    Signaling Speed



    59.84375±20ppm


    GBd

    Channel frequency

    λ

    191.3


    196.1

    THz

    Frequency offset between received carrier


    -3.6


    3.6

    GHz

    and LO

    Input power range


    -20


    13

    dBm

    Input sensitivity

    Sen

    -20



    dBm

    OSNR Tolerance




    26

    dB/0.1nm

    Optical return loss


    20



    dB

    CD Tolerance


    1200



    ps/nm

    Optical path power penalty




    0.5

    dB

    PMD tolerance


    7



    ps

    Peak PDL tolerance


    1.5



    dB

    Tolerance to change in SOP


    50



    Krad/s

    Optical input power transient tolerance


    -2


    2

    dB

    Receiver turn-up time from warm start




    10

    s

    Receiver turn-up time from cold start




    200

    s

    Intput power monitor Accuracy


    -4


    4

    dB

    Optical Rx_LOS Assert Threshold

    LOSA

    -28



    dBm

    Optical Rx_LOS Deassert Threshold

    LOSD



    -23

    dBm

    Optical Rx_LOS Hysteresis


    1


    2.5

    dBm


    QSFPDD Transceiver Electrical Pad Layout


    image.png

    image.png





    Pin Descriptions


    Pin

    Logic

    Symbol

    Description

    Plug   Sequence

    Notes

    1


    GND

    Ground

    1B

    1

    2

    CML-I

    Tx2n

    Transmitter Inverted Data   Input

    3B


    3

    CML-I

    Tx2p

    Transmitter Non-Inverted   Data Input

    3B


    4


    GND

    Ground

    1B

    1

    5

    CML-I

    Tx4n

    Transmitter Inverted Data   Input

    3B


    6

    CML-I

    Tx4p

    Transmitter Non-Inverted   Data Input

    3B


    7


    GND

    Ground

    1B

    1

    8

    LVTTL-I

    ModSelL

    Module Select

    3B


    9

    LVTTL-I

    ResetL

    Module Reset

    3B


    10


    VccRx

    +3.3V Power Supply   Receiver

    2B

    2

    11

    LVCMOS-

    I/O

    SCL

    2-wire   serial interface clock

    3B


    12

    LVCMOS-

    I/O

    SDA

    2-wire   serial interface data

    3B


    13


    GND

    Ground

    1B

    1

    14

    CML-O

    Rx3p

    Receiver Non-Inverted Data   Output

    3B


    15

    CML-O

    Rx3n

    Receiver Inverted Data   Output

    3B


    16


    GND

    Ground

    1B

    1

    17

    CML-O

    Rx1p

    Receiver Non-Inverted Data   Output

    3B


    18

    CML-O

    Rx1n

    Receiver Inverted Data   Output

    3B


    19


    GND

    Ground

    1B

    1

    20


    GND

    Ground

    1B

    1

    21

    CML-O

    Rx2n

    Receiver Inverted Data   Output

    3B


    22

    CML-O

    Rx2p

    Receiver Non-Inverted Data   Output

    3B


    23


    GND

    Ground

    1B

    1

    24

    CML-O

    Rx4n

    Receiver Inverted Data   Output

    3B


    25

    CML-O

    Rx4p

    Receiver Non-Inverted Data   Output

    3B


    26


    GND

    Ground

    1B

    1

    27

    LVTTL-O

    ModPrsL

    Module Present

    3B


    28

    LVTTL-O

    IntL

    Interrupt

    3B


    29


    VccTx

    +3.3V Power supply   transmitter

    2B

    2

    30


    Vcc1

    +3.3V Power supply

    2B

    2

    31

    LVTTL-I

    LPMode

    Low Power Mode

    3B


    32


    GND

    Ground

    1B

    1

    33

    CML-I

    Tx3p

    Transmitter Non-Inverted   Data Input

    3B


    34

    CML-I

    Tx3n

    Transmitter Inverted Data   Input

    3B


    35


    GND

    Ground

    1B

    1

    36

    CML-I

    Tx1p

    Transmitter Non-Inverted   Data Input

    3B


    37

    CML-I

    Tx1n

    Transmitter Inverted Data   Input

    3B



    38


    GND

    Ground

    1B

    1

    39


    GND

    Ground

    1A

    1

    40

    CML-I

    Tx6n

    Transmitter Inverted Data   Input

    3A


    41

    CML-I

    Tx6p

    Transmitter Non-Inverted   Data Input

    3A


    42


    GND

    Ground

    1A

    1

    43

    CML-I

    Tx8n

    Transmitter Inverted Data   Input

    3A


    44

    CML-I

    Tx8p

    Transmitter Non-Inverted   Data Input

    3A


    45


    GND

    Ground

    1A

    1

    46


    Reserved

    For future use

    3A

    3

    47


    VS1

    Module Vendor Specific 1

    3A

    3

    48


    VccRx1

    3.3V Power Supply

    2A

    2

    49


    VS2

    Module Vendor Specific 2

    3A

    3

    50


    VS3

    Module Vendor Specific 3

    3A

    3

    51


    GND

    Ground

    1A

    1

    52

    CML-O

    Rx7p

    Receiver Non-Inverted Data   Output

    3A


    53

    CML-O

    Rx7n

    Receiver Inverted Data   Output

    3A


    54


    GND

    Ground

    1A

    1

    55

    CML-O

    Rx5p

    Receiver Non-Inverted Data   Output

    3A


    56

    CML-O

    Rx5n

    Receiver Inverted Data   Output

    3A


    57


    GND

    Ground

    1A

    1

    58


    GND

    Ground

    1A

    1

    59

    CML-O

    Rx6n

    Receiver Inverted Data   Output

    3A


    60

    CML-O

    Rx6p

    Receiver Non-Inverted Data   Output

    3A


    61


    GND

    Ground

    1A

    1

    62

    CML-O

    Rx8n

    Receiver Inverted Data   Output

    3A


    63

    CML-O

    Rx8p

    Receiver Non-Inverted Data   Output

    3A


    64


    GND

    Ground

    1A

    1

    65


    NC

    No Connect

    3A

    3

    66


    Reserved

    For future use

    3A

    3

    67


    VccTx1

    3.3V Power Supply

    2A

    2

    68


    Vcc2

    3.3V Power Supply

    2A

    2

    69


    Reserved

    For Future Use

    3A

    3

    70


    GND

    Ground

    1A

    1

    71

    CML-I

    Tx7p

    Transmitter Non-Inverted Data Input

    3A


    72

    CML-I

    Tx7n

    Transmitter Inverted Data   Input

    3A


    73


    GND

    Ground

    1A

    1

    74

    CML-I

    Tx5p

    Transmitter Non-Inverted   Data Input

    3A


    75

    CML-I

    Tx5n

    Transmitter Inverted Data   Input

    3A


    76


    GND

    Ground

    1A

    1

    1: QSFP-DD uses common ground (GND) for all signals and supply (power).   All are common within the QSFP-DD module and all module voltages are   referenced to this potential unless otherwise noted.

    Connect these directly to the host board   signal-common ground plane.



    2: VccRx, VccRx1, Vcc1,   Vcc2, VccTx and VccTx1 shall be applied concurrently. VccRx, VccRx1, Vcc1,   Vcc2, VccTx and VccTx1 may be internally connected within the module in any   combination. The

    connector Vcc pins are each rated for a maximum   current of 1000 mA.

    3: All Vendor Specific, Reserved and No Connect pins may be   terminated with 50 ohms to ground on the host. Pad 65 (No Connect) shall be   left unconnected within the module. Vendor specific and

    Reserved   pads shall have an impedance to GND that is greater than 10 k Ohms and less   than 100 pF.

    4: Plug Sequence specifies   the mating sequence of the host connector and module. The sequence is 1A, 2A,   3A, 1B, 2B, 3B. Contact sequence A will make, then break contact with   additional QSFP-DD pads.

    Sequence 1A, 1B will then occur simultaneously,   followed by 2A, 2B, followed by 3A, 3B.

    image.png


    Figure 7: Host Board Power Supply Filter

    During power transient events, the host should ensure that any neighboring modules sharing the same supply stay within their specified supply voltage limits. The host should also ensure that the intrinsic noise of the power rail is filtered in order to guarantee the correct operation of the optical modules. The reference power supply filter is shown in Figure 7.


  • Mechanical Specification

    image.png

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